Scott Rixner

Latest

• An FPGA Accelerator for Genome Variant Calling
• Understanding Transparent Superpage Management
• Virtflex: Automatic Adaptation to NUMA Topology Change for OpenMP Applications
• A Comprehensive Analysis of Superpage Management Mechanisms and Policies
• Compigorithm: An Interactive Tool for Guided Practice of Complexity Analysis
• Design and Evaluation of a Collaborative Online Computational Thinking Course
• Auto-Generating Visual Exercises for Learning Program Semantics
• The Error Landscape: Characterizing the Mistakes of Novice Programmers
• A Policy-Based System for Dynamic Scaling of Virtual Machine Memory Reservations
• An Automated System for Interactively Learning Software Testing
• Data-Driven Test Case Generation for Automated Programming Assessment
• Leveraging Managed Runtime Systems to Build, Analyze, and Optimize Memory Graphs
• TPC: Target-Driven Parallelism Combining Prediction and Correction to Reduce Tail Latency in Interactive Services
• Scalable Multi-Failure Fast Failover via Forwarding Table Compression
• Surviving Peripheral Failures in Embedded Systems
• Grading the Graders: Motivating Peer Graders in a MOOC
• Owl: A Python-based toolchain and runtime system for small embedded systems
• System and Method for Managing Input/Output Data of Peripheral Devices
• Learning to Grade Student Programs in a Massive Open Online Course
• Predictive Parallelization: Taming Tail Latencies in Web Search
• Medusa: Managing Concurrency and Communication in Embedded Systems
• Method and System for Scalable Ethernet
• An Environment for Learning Interactive Programming
• Facilitating Human Interaction in an Online Programming Course
• Reducing DRAM Row Activations with Eager Read/Write Clustering
• Plinko: Building Provably Resilient Forwarding Tables
• Hyper-Switch: A Scalable Software Virtual Switching Architecture
• Hyper-Switch: A Scalable Software Virtual Switching Architecture
• Adaptive Parallelism for Web Search
• The Owl Embedded Python Environment: Microcontroller Development for the Modern World
• Design and Implementation of an Embedded Python Run-Time System
• A Scalability Study of Network Enterprise Architectures
• System and Method for Context-independent Codes for Off-chip Interconnects
• SpecTLB: A Mechanism for Speculative Address Translation
• A Low-Cost Multi-Robot System for Research, Teaching, and Outreach
• Axon: A Flexible Substrate for Source-routed Ethernet
• sNICh: Efficient Last Hop Networking in the Data Center
• System and Method for Performing Efficient ConditionalVector Operations For Data Parallel Architectures InvolvingBoth Input and Conditional Vector Values
• Translation Caching: Skip, Don't Walk (the Page Table)
• System and Method for Re-ordering Memory References forAccess to Memory
• The Hadoop Distributed Filesystem: Balancing Portability and Performance
• The Axon Network Device: Prototyping with NetFPGA
• Achieving 10Gbps Using Safe and Transparent Network Interface Virtualization
• Protection Strategies for Direct Access to Virtualized I/O Devices
• Explaining the Impact of Network Transport Protocols on SIP Proxy Performance
• Scheduling I/O in Virtual Machine Monitors
• Network Virtualization: Breaking the Performance Barrier
• Parallel Programmable Ethernet Controllers: Performance and Security
• RiceNIC: A Reconfigurable Network Interface for Experimental Research and Education
• RiceNIC: Prototyping Network Interfaces
• System and Method for Re-ordering Memory References forAccess to Memory
• Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory
• Concurrent Direct Network Access for Virtual Machine Monitors
• A Reconfigurable and Programmable Gigabit Ethernet Network Interface Card
• Connection Handoff Policies for TCP Offload Network Interfaces
• Dependable $neq$ Unaffordable
• An Evaluation of Network Stack Parallelization Strategies in Modern Operating Systems
• System and Method for Performing Efficient ConditionalVector Operations For Data Parallel Architectures InvolvingBoth Input and Conditional Vector Values
• System and Method for Re-ordering Memory References forAccess to Memory
• An Evaluation of Network Stack Parallelization Strategies in Modern Operating Systems
• TCP Offload through Connection Handoff
• Parallelization Strategies for Network Interface Firmware
• Optimizing Kernel Block Memory Operations
• Network Stack Parallelization Strategies for Modern Multiprocessors
• Context-independent codes for off-chip interconnects
• Context-Independent Codes for Off-Chip Interconnects
• Network Interface Data Caching
• Performance Characterization of the FreeBSD Network Stack
• An Efficient Programmable 10 Gigabit Ethernet Network Interface Card
• Context-independent Codes for Off-chip Interconnects
• Improving Power Efficiency in Stream Processors through Dynamic Cluster Reconfiguration
• Memory Controller Optimizations for Web Servers
• An Event-driven Architecture for MPI Libraries
• Comparing Ethernet and Myrinet for MPI Communication
• Design Space Exploration for Real-Time Embedded Stream Processors
• Isolating the Performance Impacts of Network Interface Cards through Microbenchmarks
• Isolating the Performance Impacts of Network Interface Cards Through Microbenchmarks
• Programmable Stream Processors
• Exploiting Task-level Concurrency in a Programmable Network Interface
• Exploring the VLSI Scalability of Stream Processors
• Increasing Web Server Throughput with Network Interface Data Caching
• A Stream Processor Development Platform
• Media Processing Applications on the Imagine Stream Processor
• The Imagine Stream Processor
• A Programmable Baseband Processor Design for Software Defined Radios
• System and Method for Implementing Conditional VectorOperations in Which an Input Vector Containing MultipleOperands to Be Used in Conditional Operations Is DividedInto Two Or More Output Vectors Based on a ConditionVector
• Imagine: Media Processing with Streams
• System and Method for Performing Compound Vector Operations
• A Bandwidth-efficient Architecture for a Streaming Media Processor
• Stream Processor Architecture
• Efficient Conditional Operations for Data-parallel Architectures
• Communication Scheduling
• Imagine: Signal and Image Processing Using Streams
• Polygon Rendering on a Stream Architecture
• Memory Access Scheduling
• Apparatus for performing real time caching utilizing an execution quantization timer and an interrupt controller
• Register Organization for Media Processing
• Imagine: A High-Performance, Power-Efficient Signal Processor
• A Bandwidth-Efficient Architecture for Media Processing
• Memory System Architecture for Real-Time Multitasking Systems