opd_ibs_trans.c

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00001 
00014 #include "opd_ibs.h"
00015 #include "opd_ibs_macro.h"
00016 #include "opd_ibs_trans.h"
00017 #include "opd_trans.h"
00018 #include "opd_printf.h"
00019 
00020 #include <stdlib.h>
00021 #include <stdio.h>
00022 
00023 extern FILE * bta_log;
00024 extern FILE * memaccess_log;
00025 
00026 /*
00027  * --------------------- FETCH DERIVED FUNCTION
00028  */
00029 void trans_ibs_fetch (struct transient * trans, unsigned int selected_flag)
00030 {
00031     struct ibs_fetch_sample * trans_fetch = ((struct ibs_sample*)(trans->ext))->fetch;
00032 
00033     if ((selected_flag) == 0)
00034         return;
00035 
00036     CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_ALL) {
00037         /* IBS all fetch samples (kills + attempts) */
00038         AGG_IBS_EVENT(DE_IBS_FETCH_ALL);
00039     }       
00040 
00041     CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_KILLED) {
00042         /* IBS killed fetches ("case 0") -- All interesting event
00043          * flags are clear */
00044         if (IBS_FETCH_KILLED(trans_fetch))
00045             AGG_IBS_EVENT(DE_IBS_FETCH_KILLED);
00046     }
00047 
00048     CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_ATTEMPTED) {
00049         /* Any non-killed fetch is an attempted fetch */
00050         AGG_IBS_EVENT(DE_IBS_FETCH_ATTEMPTED);
00051     }
00052 
00053     CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_COMPLETED) {
00054         if (IBS_FETCH_FETCH_COMPLETION(trans_fetch))
00055             /* IBS Fetch Completed */
00056             AGG_IBS_EVENT(DE_IBS_FETCH_COMPLETED);
00057     }
00058 
00059     CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_ABORTED) {
00060         if (!IBS_FETCH_FETCH_COMPLETION(trans_fetch))
00061             /* IBS Fetch Aborted */
00062             AGG_IBS_EVENT(DE_IBS_FETCH_ABORTED);
00063     }
00064 
00065     CHECK_FETCH_SELECTED_FLAG(DE_IBS_L1_ITLB_HIT) {
00066         /* IBS L1 ITLB hit */
00067         if (IBS_FETCH_L1_TLB_HIT(trans_fetch))
00068             AGG_IBS_EVENT(DE_IBS_L1_ITLB_HIT);
00069     }
00070 
00071     CHECK_FETCH_SELECTED_FLAG(DE_IBS_ITLB_L1M_L2H) {
00072         /* IBS L1 ITLB miss and L2 ITLB hit */
00073         if (IBS_FETCH_ITLB_L1M_L2H(trans_fetch))
00074             AGG_IBS_EVENT(DE_IBS_ITLB_L1M_L2H);
00075     }
00076 
00077     CHECK_FETCH_SELECTED_FLAG(DE_IBS_ITLB_L1M_L2M) {
00078         /* IBS L1 & L2 ITLB miss; complete ITLB miss */
00079         if (IBS_FETCH_ITLB_L1M_L2M(trans_fetch))
00080             AGG_IBS_EVENT(DE_IBS_ITLB_L1M_L2M);
00081     }
00082 
00083     CHECK_FETCH_SELECTED_FLAG(DE_IBS_IC_MISS) {
00084         /* IBS instruction cache miss */
00085         if (IBS_FETCH_INST_CACHE_MISS(trans_fetch))
00086             AGG_IBS_EVENT(DE_IBS_IC_MISS);
00087     }
00088 
00089     CHECK_FETCH_SELECTED_FLAG(DE_IBS_IC_HIT) {
00090         /* IBS instruction cache hit */
00091         if (IBS_FETCH_INST_CACHE_HIT(trans_fetch))
00092             AGG_IBS_EVENT(DE_IBS_IC_HIT);
00093     }
00094 
00095     CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_4K_PAGE) {
00096         if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch)
00097             && IBS_FETCH_TLB_PAGE_SIZE_4K(trans_fetch))
00098             AGG_IBS_EVENT(DE_IBS_FETCH_4K_PAGE);
00099     }
00100 
00101     CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_2M_PAGE) {
00102         if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch)
00103             && IBS_FETCH_TLB_PAGE_SIZE_2M(trans_fetch))
00104             AGG_IBS_EVENT(DE_IBS_FETCH_2M_PAGE);
00105     }
00106 
00107     CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_1G_PAGE) {
00108         if (IBS_FETCH_PHYS_ADDR_VALID(trans_fetch)
00109             && IBS_FETCH_TLB_PAGE_SIZE_1G(trans_fetch))
00110             AGG_IBS_EVENT(DE_IBS_FETCH_1G_PAGE);
00111     }
00112 
00113     CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_XX_PAGE) {
00114     }
00115 
00116     CHECK_FETCH_SELECTED_FLAG(DE_IBS_FETCH_LATENCY) {
00117         if (IBS_FETCH_FETCH_LATENCY(trans_fetch))
00118             AGG_IBS_COUNT(DE_IBS_FETCH_LATENCY,
00119                       IBS_FETCH_FETCH_LATENCY(trans_fetch));
00120     }
00121 }
00122 
00123 
00124 /*
00125  * --------------------- OP DERIVED FUNCTION
00126  */
00127 void trans_ibs_op (struct transient * trans, unsigned int selected_flag)
00128 {
00129     struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
00130 
00131     if ((selected_flag) == 0)
00132         return;
00133 
00134     CHECK_OP_SELECTED_FLAG(DE_IBS_OP_ALL) {
00135         /* All IBS op samples */
00136         AGG_IBS_EVENT(DE_IBS_OP_ALL);
00137     }
00138 
00139     CHECK_OP_SELECTED_FLAG(DE_IBS_OP_TAG_TO_RETIRE) {
00140         /* Tally retire cycle counts for all sampled macro-ops
00141          * IBS tag to retire cycles */
00142         if (IBS_OP_TAG_TO_RETIRE_CYCLES(trans_op))
00143             AGG_IBS_COUNT(DE_IBS_OP_TAG_TO_RETIRE,
00144                 IBS_OP_TAG_TO_RETIRE_CYCLES(trans_op));
00145     }
00146 
00147     CHECK_OP_SELECTED_FLAG(DE_IBS_OP_COMP_TO_RETIRE) {
00148         /* IBS completion to retire cycles */
00149         if (IBS_OP_COM_TO_RETIRE_CYCLES(trans_op))
00150             AGG_IBS_COUNT(DE_IBS_OP_COMP_TO_RETIRE,
00151                 IBS_OP_COM_TO_RETIRE_CYCLES(trans_op));
00152     }
00153 
00154     CHECK_OP_SELECTED_FLAG(DE_IBS_BRANCH_RETIRED) {
00155         if (IBS_OP_BRANCH_RETIRED(trans_op))
00156             /* IBS Branch retired op */
00157             AGG_IBS_EVENT(DE_IBS_BRANCH_RETIRED) ;
00158     }
00159 
00160     CHECK_OP_SELECTED_FLAG(DE_IBS_BRANCH_MISP) {
00161         if (IBS_OP_BRANCH_RETIRED(trans_op)
00162             /* Test branch-specific event flags */
00163             /* IBS mispredicted Branch op */
00164             && IBS_OP_BRANCH_MISPREDICT(trans_op))
00165             AGG_IBS_EVENT(DE_IBS_BRANCH_MISP) ;
00166     }
00167 
00168     CHECK_OP_SELECTED_FLAG(DE_IBS_BRANCH_TAKEN) {
00169         if (IBS_OP_BRANCH_RETIRED(trans_op)
00170             /* IBS taken Branch op */
00171             && IBS_OP_BRANCH_TAKEN(trans_op))
00172             AGG_IBS_EVENT(DE_IBS_BRANCH_TAKEN);
00173     }
00174 
00175     CHECK_OP_SELECTED_FLAG(DE_IBS_BRANCH_MISP_TAKEN) {
00176         if (IBS_OP_BRANCH_RETIRED(trans_op)
00177             /* IBS mispredicted taken branch op */
00178             && IBS_OP_BRANCH_TAKEN(trans_op)
00179             && IBS_OP_BRANCH_MISPREDICT(trans_op))
00180             AGG_IBS_EVENT(DE_IBS_BRANCH_MISP_TAKEN);
00181     }
00182 
00183     CHECK_OP_SELECTED_FLAG(DE_IBS_RETURN) {
00184         if (IBS_OP_BRANCH_RETIRED(trans_op)
00185             /* IBS return op */
00186             && IBS_OP_RETURN(trans_op))
00187             AGG_IBS_EVENT(DE_IBS_RETURN);
00188     }
00189 
00190     CHECK_OP_SELECTED_FLAG(DE_IBS_RETURN_MISP) {
00191         if (IBS_OP_BRANCH_RETIRED(trans_op)
00192             /* IBS mispredicted return op */
00193             && IBS_OP_RETURN(trans_op)
00194             && IBS_OP_BRANCH_MISPREDICT(trans_op))
00195             AGG_IBS_EVENT(DE_IBS_RETURN_MISP);
00196     }
00197 
00198     CHECK_OP_SELECTED_FLAG(DE_IBS_RESYNC) {
00199         /* Test for a resync macro-op */
00200         if (IBS_OP_BRANCH_RESYNC(trans_op))
00201             AGG_IBS_EVENT(DE_IBS_RESYNC);
00202     }
00203 }
00204 
00205 
00206 /*
00207  * --------------------- OP LS DERIVED FUNCTION
00208  */
00209 void trans_ibs_op_ls (struct transient * trans, unsigned int selected_flag)
00210 {
00211     struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
00212 
00213     /* Preliminary check */
00214     if (!IBS_OP_IBS_LD_OP(trans_op) && !IBS_OP_IBS_ST_OP(trans_op))
00215         return;
00216 
00217 
00218     if ((selected_flag) == 0)
00219         return;
00220 
00221     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_ALL_OP) {
00222         /* Count the number of LS op samples */
00223         AGG_IBS_EVENT(DE_IBS_LS_ALL_OP) ;
00224     }
00225 
00226     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_LOAD_OP) {
00227         if (IBS_OP_IBS_LD_OP(trans_op))
00228             /* TALLy an IBS load derived event */
00229             AGG_IBS_EVENT(DE_IBS_LS_LOAD_OP) ;
00230     }
00231 
00232     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_STORE_OP) {
00233         if (IBS_OP_IBS_ST_OP(trans_op))
00234             /* Count and handle store operations */
00235             AGG_IBS_EVENT(DE_IBS_LS_STORE_OP);
00236     }
00237 
00238     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DTLB_L1H) {
00239         if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
00240             && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op))
00241             /* L1 DTLB hit -- This is the most frequent case */
00242             AGG_IBS_EVENT(DE_IBS_LS_DTLB_L1H);
00243     }
00244 
00245     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DTLB_L1M_L2H) {
00246         /* l2_translation_size = 1 */
00247         if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
00248             && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
00249             && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op))
00250             /* L1 DTLB miss, L2 DTLB hit */
00251             AGG_IBS_EVENT(DE_IBS_LS_DTLB_L1M_L2H);
00252     }
00253 
00254     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DTLB_L1M_L2M) {
00255         if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
00256             && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
00257             && IBS_OP_IBS_DC_L2_TLB_MISS(trans_op))
00258             /* L1 DTLB miss, L2 DTLB miss */
00259             AGG_IBS_EVENT(DE_IBS_LS_DTLB_L1M_L2M);
00260     }
00261 
00262     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DC_MISS) {
00263         if (IBS_OP_IBS_DC_MISS(trans_op))
00264             AGG_IBS_EVENT(DE_IBS_LS_DC_MISS);
00265     }
00266 
00267     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DC_HIT) {
00268         if (!IBS_OP_IBS_DC_MISS(trans_op))
00269             AGG_IBS_EVENT(DE_IBS_LS_DC_HIT);
00270     }
00271 
00272     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_MISALIGNED) {
00273         if (IBS_OP_IBS_DC_MISS_ACC(trans_op))
00274             AGG_IBS_EVENT(DE_IBS_LS_MISALIGNED);
00275     }
00276 
00277     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_BNK_CONF_LOAD) {
00278         if (IBS_OP_IBS_DC_LD_BNK_CON(trans_op))
00279             AGG_IBS_EVENT(DE_IBS_LS_BNK_CONF_LOAD);
00280     }
00281 
00282     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_BNK_CONF_STORE) {
00283         if (IBS_OP_IBS_DC_ST_BNK_CON(trans_op))
00284             AGG_IBS_EVENT(DE_IBS_LS_BNK_CONF_STORE);
00285     }
00286 
00287     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_STL_FORWARDED) {
00288         if (IBS_OP_IBS_LD_OP(trans_op)
00289             /* Data forwarding info are valid only for load ops */
00290             && IBS_OP_IBS_DC_ST_TO_LD_FWD(trans_op))
00291             AGG_IBS_EVENT(DE_IBS_LS_STL_FORWARDED) ;
00292     }
00293 
00294     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_STL_CANCELLED) {
00295         if (IBS_OP_IBS_LD_OP(trans_op))
00296         if (IBS_OP_IBS_DC_ST_TO_LD_CAN(trans_op))
00297             AGG_IBS_EVENT(DE_IBS_LS_STL_CANCELLED) ;
00298     }
00299 
00300     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_UC_MEM_ACCESS) {
00301         if (IBS_OP_IBS_DC_UC_MEM_ACC(trans_op))
00302             AGG_IBS_EVENT(DE_IBS_LS_UC_MEM_ACCESS);
00303     }
00304 
00305     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_WC_MEM_ACCESS) {
00306         if (IBS_OP_IBS_DC_WC_MEM_ACC(trans_op))
00307             AGG_IBS_EVENT(DE_IBS_LS_WC_MEM_ACCESS);
00308     }
00309 
00310     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_LOCKED_OP) {
00311         if (IBS_OP_IBS_LOCKED_OP(trans_op))
00312             AGG_IBS_EVENT(DE_IBS_LS_LOCKED_OP);
00313     }
00314 
00315     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_MAB_HIT) {
00316         if (IBS_OP_IBS_DC_MAB_HIT(trans_op))
00317             AGG_IBS_EVENT(DE_IBS_LS_MAB_HIT);
00318     }
00319 
00320     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L1_DTLB_4K) {
00321         /* l1_translation */
00322         if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
00323             && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
00324 
00325             && !IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op)
00326             && !IBS_OP_IBS_DC_L1_TLB_HIT_1GB(trans_op))
00327             /* This is the most common case, unfortunately */
00328             AGG_IBS_EVENT(DE_IBS_LS_L1_DTLB_4K) ;
00329     }
00330 
00331     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L1_DTLB_2M) {
00332         /* l1_translation */
00333         if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
00334             && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
00335 
00336             && IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op))
00337             /* 2M L1 DTLB page translation */
00338             AGG_IBS_EVENT(DE_IBS_LS_L1_DTLB_2M);
00339     }
00340 
00341     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L1_DTLB_1G) {
00342         /* l1_translation */
00343         if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
00344             && !IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
00345 
00346             && !IBS_OP_IBS_DC_L1_TLB_HIT_2MB(trans_op)
00347             && IBS_OP_IBS_DC_L1_TLB_HIT_1GB(trans_op))
00348             /* 1G L1 DTLB page translation */
00349             AGG_IBS_EVENT(DE_IBS_LS_L1_DTLB_1G);
00350     }
00351 
00352     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L1_DTLB_RES) {
00353     }
00354 
00355     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L2_DTLB_4K) {
00356         /* l2_translation_size = 1 */
00357         if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
00358             && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
00359             && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)
00360 
00361             /* L2 DTLB page translation */
00362             && !IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
00363             && !IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
00364             /* 4K L2 DTLB page translation */
00365             AGG_IBS_EVENT(DE_IBS_LS_L2_DTLB_4K);
00366     }
00367 
00368     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L2_DTLB_2M) {
00369         /* l2_translation_size = 1 */
00370         if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
00371             && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
00372             && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)
00373 
00374             /* L2 DTLB page translation */
00375             && IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
00376             && !IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
00377             /* 2M L2 DTLB page translation */
00378             AGG_IBS_EVENT(DE_IBS_LS_L2_DTLB_2M);
00379     }
00380 
00381     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L2_DTLB_1G) {
00382         /* l2_translation_size = 1 */
00383         if (IBS_OP_IBS_DC_LIN_ADDR_VALID(trans_op)
00384             && IBS_OP_IBS_DC_L1_TLB_MISS(trans_op)
00385             && !IBS_OP_IBS_DC_L2_TLB_MISS(trans_op)
00386 
00387             /* L2 DTLB page translation */
00388             && !IBS_OP_IBS_DC_L2_TLB_HIT_2MB(trans_op)
00389             && IBS_OP_IBS_DC_L2_TLB_HIT_1GB(trans_op))
00390             /* 2M L2 DTLB page translation */
00391             AGG_IBS_EVENT(DE_IBS_LS_L2_DTLB_1G);
00392     }
00393 
00394     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_L2_DTLB_RES2) {
00395     }
00396 
00397     CHECK_OP_LS_SELECTED_FLAG(DE_IBS_LS_DC_LOAD_LAT) {
00398         if (IBS_OP_IBS_LD_OP(trans_op)
00399             /* If the load missed in DC, tally the DC load miss latency */
00400             && IBS_OP_IBS_DC_MISS(trans_op))
00401             /* DC load miss latency is only reliable for load ops */
00402             AGG_IBS_COUNT(DE_IBS_LS_DC_LOAD_LAT,
00403                       IBS_OP_DC_MISS_LATENCY(trans_op)) ;
00404     }
00405 }
00406 
00407 /*
00408  * --------------------- OP NB DERIVED FUNCTION
00409  *
00410  * NB data is only guaranteed reliable for load operations
00411  * that miss in L1 and L2 cache. NB data arrives too late
00412  * to be reliable for store operations
00413  */
00414 void trans_ibs_op_nb (struct transient * trans, unsigned int selected_flag)
00415 {
00416     struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
00417 
00418     /* Preliminary check */
00419     if ((selected_flag) == 0)
00420         return;
00421 
00422     if (!IBS_OP_IBS_LD_OP(trans_op))
00423         return;
00424 
00425     if (!IBS_OP_IBS_DC_MISS(trans_op))
00426         return;
00427 
00428     if (IBS_OP_NB_IBS_REQ_SRC(trans_op) == 0)
00429         return;
00430 
00431     CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_LOCAL) {
00432         if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op))
00433             /* Request was serviced by local processor */
00434             AGG_IBS_EVENT(DE_IBS_NB_LOCAL) ;
00435     }
00436 
00437     CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_REMOTE) {
00438         if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op))
00439             /* Request was serviced by remote processor */
00440             AGG_IBS_EVENT(DE_IBS_NB_REMOTE) ;
00441     }
00442 
00443     CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_LOCAL_L3) {
00444         if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
00445             &&  IBS_OP_NB_IBS_REQ_SRC_01(trans_op))
00446             AGG_IBS_EVENT(DE_IBS_NB_LOCAL_L3);
00447     }
00448 
00449     CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_LOCAL_CACHE) {
00450         if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
00451             &&  IBS_OP_NB_IBS_REQ_SRC_02(trans_op))
00452             AGG_IBS_EVENT(DE_IBS_NB_LOCAL_CACHE);
00453     }
00454 
00455     CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_REMOTE_CACHE) {
00456         if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
00457             &&  IBS_OP_NB_IBS_REQ_SRC_02(trans_op))
00458             AGG_IBS_EVENT(DE_IBS_NB_REMOTE_CACHE) ;
00459     }
00460 
00461     CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_LOCAL_DRAM) {
00462         if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
00463             &&  IBS_OP_NB_IBS_REQ_SRC_03(trans_op))
00464             AGG_IBS_EVENT(DE_IBS_NB_LOCAL_DRAM);
00465     }
00466 
00467     CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_REMOTE_DRAM) {
00468         if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
00469             &&  IBS_OP_NB_IBS_REQ_SRC_03(trans_op))
00470             AGG_IBS_EVENT(DE_IBS_NB_REMOTE_DRAM) ;
00471     }
00472 
00473     CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_LOCAL_OTHER) {
00474         if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
00475             &&  IBS_OP_NB_IBS_REQ_SRC_07(trans_op))
00476             AGG_IBS_EVENT(DE_IBS_NB_LOCAL_OTHER);
00477     }
00478 
00479     CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_REMOTE_OTHER) {
00480         if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op)
00481             &&  IBS_OP_NB_IBS_REQ_SRC_07(trans_op))
00482             AGG_IBS_EVENT(DE_IBS_NB_REMOTE_OTHER) ;
00483     }
00484 
00485     CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_CACHE_STATE_M) {
00486         if (IBS_OP_NB_IBS_REQ_SRC_02(trans_op)
00487             && !IBS_OP_NB_IBS_CACHE_HIT_ST(trans_op))
00488             AGG_IBS_EVENT(DE_IBS_NB_CACHE_STATE_M) ;
00489     }
00490 
00491     CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_CACHE_STATE_O) {
00492         if (IBS_OP_NB_IBS_REQ_SRC_02(trans_op)
00493             && IBS_OP_NB_IBS_CACHE_HIT_ST(trans_op))
00494             AGG_IBS_EVENT(DE_IBS_NB_CACHE_STATE_O) ;
00495     }
00496 
00497     CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_LOCAL_LATENCY) {
00498         if (!IBS_OP_NB_IBS_REQ_DST_PROC(trans_op))
00499             /* Request was serviced by local processor */
00500             AGG_IBS_COUNT(DE_IBS_NB_LOCAL_LATENCY,
00501                       IBS_OP_DC_MISS_LATENCY(trans_op));
00502     }
00503 
00504     CHECK_OP_NB_SELECTED_FLAG(DE_IBS_NB_REMOTE_LATENCY) {
00505         if (IBS_OP_NB_IBS_REQ_DST_PROC(trans_op))
00506             /* Request was serviced by remote processor */
00507             AGG_IBS_COUNT(DE_IBS_NB_REMOTE_LATENCY,
00508                       IBS_OP_DC_MISS_LATENCY(trans_op));
00509     }
00510 }
00511 
00512 
00513 int trans_ibs_op_rip_invalid (struct transient * trans)
00514 {
00515     struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
00516 
00517     if (IBS_OP_RIP_INVALID(trans_op))
00518         return 1;   
00519 
00520     return 0;
00521 }
00522 
00523 
00524 void trans_ibs_op_mask_reserved (unsigned int family, struct transient * trans)
00525 {
00526     struct ibs_op_sample * trans_op    = ((struct ibs_sample*)(trans->ext))->op;
00527 
00528     switch (family) {
00529     case 0x10:
00530         /* Reserved IbsRipInvalid (MSRC001_1035[38])*/
00531         trans_op->ibs_op_data1_high &= ~MASK_RIP_INVALID;
00532         break;
00533     case 0x12:
00534         /* Reserved NbIbsReqDstProc (MSRCC001_1036[4]) */
00535         trans_op->ibs_op_data2_low &= ~NB_MASK_REQ_DST_PROC;
00536         /* Reserved NbIbsReqCacheHitSt (MSRCC001_1036[5]) */
00537         trans_op->ibs_op_data2_low &= ~NB_MASK_L3_STATE;
00538         break;
00539     case 0x14:
00540         /* Reserved NbIbsReqDstProc (MSRCC001_1036[4]) */
00541         trans_op->ibs_op_data2_low &= ~NB_MASK_REQ_DST_PROC;
00542         /* Reserved NbIbsReqCacheHitSt (MSRCC001_1036[5]) */
00543         trans_op->ibs_op_data2_low &= ~NB_MASK_L3_STATE;
00544         /* Reserved IbsDcL1tlbHit1G (MSRC001_1037[5]) */
00545         trans_op->ibs_op_data3_low &= ~DC_MASK_L1_HIT_1G;
00546         /* Reserved IbsDcLdBnkCon (MSRC001_1037[9]) */
00547         trans_op->ibs_op_data3_low &= ~DC_MASK_LD_BANK_CONFLICT;
00548         /* Reserved IbsDcStBnkCon (MSRC001_1037[10]) */
00549         trans_op->ibs_op_data3_low &= ~DC_MASK_ST_BANK_CONFLICT;
00550         /* Reserved IbsDcStToLdCan (MSRC001_1037[12]) */
00551         trans_op->ibs_op_data3_low &= ~DC_MASK_ST_TO_LD_CANCEL;
00552         /* Reserved IbsDcL2tlbHit1G (MSRC001_1037[19]) */
00553         trans_op->ibs_op_data3_low &= ~DC_MASK_L2_HIT_1G;
00554         
00555         break;
00556     case 0x15:
00557     default:
00558         break;
00559     
00560     }
00561 }
00562 
00563 
00564 void trans_ibs_op_bta(struct transient * trans)
00565 {
00566     static cookie_t old_cookie     = NO_COOKIE;
00567     static cookie_t old_app_cookie = NO_COOKIE;
00568     struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
00569 
00570     if (!bta_log)
00571         return;
00572 
00573     if (!trans_op->ibs_op_brtgt_addr)
00574         return;
00575 
00576     if( old_app_cookie == INVALID_COOKIE 
00577     ||  old_app_cookie == NO_COOKIE 
00578     ||  old_app_cookie != trans->app_cookie) {
00579         old_app_cookie = trans->cookie;
00580     }
00581 
00582     if (trans->in_kernel == 1) {
00583         old_cookie = NO_COOKIE;
00584     } else {
00585         if( old_cookie == INVALID_COOKIE 
00586         ||  old_cookie == NO_COOKIE 
00587         ||  old_cookie != trans->cookie) {
00588             old_cookie = trans->cookie;
00589         }
00590     }
00591 
00592     fprintf(bta_log, "0x%016llx,0x%016llx,%02lu %08u,%08u,0x%08x,0x%08lx\n",
00593                         trans->app_cookie, trans->cookie, trans->cpu, trans->tgid, trans->tid, (unsigned int)trans->pc,
00594             trans_op->ibs_op_brtgt_addr);
00595 }
00596 
00597 
00598 void trans_ibs_op_ls_memaccess(struct transient * trans)
00599 {
00600     static cookie_t old_cookie     = NO_COOKIE;
00601     static cookie_t old_app_cookie = NO_COOKIE;
00602     struct ibs_op_sample * trans_op = ((struct ibs_sample*)(trans->ext))->op;
00603 
00604     if (!memaccess_log)
00605         return;
00606 
00607     if( old_app_cookie == INVALID_COOKIE 
00608     ||  old_app_cookie == NO_COOKIE 
00609     ||  old_app_cookie != trans->app_cookie) {
00610         old_app_cookie = trans->cookie;
00611     }
00612 
00613     if (trans->in_kernel == 1) {
00614         old_cookie = NO_COOKIE;
00615     } else {
00616         if( old_cookie == INVALID_COOKIE 
00617         ||  old_cookie == NO_COOKIE 
00618         ||  old_cookie != trans->cookie) {
00619             old_cookie = trans->cookie;
00620         }
00621     }
00622 
00623     fprintf(memaccess_log, "0x%016llx,0x%016llx,%02lu,%08u,%08u,0x%08x,0x%08u:%08x,0x%08x:%08x,%s,%08u\n",
00624                         trans->app_cookie, 
00625 trans->cookie, 
00626 trans->cpu, 
00627 trans->tgid, 
00628 trans->tid, 
00629 (unsigned int)trans->pc, 
00630             trans_op->ibs_op_phys_addr_high, trans_op->ibs_op_phys_addr_low, 
00631             trans_op->ibs_op_ldst_linaddr_high, trans_op->ibs_op_ldst_linaddr_low, 
00632             (IBS_OP_IBS_LD_OP(trans_op))? "LD": "ST", 
00633             (unsigned int) IBS_OP_DC_MISS_LATENCY(trans_op));
00634 }

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