pmu_x86.h

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#ifndef __PMU_X86_H__
#define __PMU_X86_H__

#include <utilities/arch/cpuid.h>

struct pmu_config_s {
  cpu_type_t cpu;
  const char *event;
};

struct pmu_config_s pmu_events[] = {
    {INTEL_SNB, "MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD"},
    {INTEL_SNB, "MEM_TRANS_RETIRED:PRECISE_STORE"},

    {INTEL_SNB_EP, "MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD"},
    {INTEL_SNB_EP, "MEM_TRANS_RETIRED:PRECISE_STORE"},

    {INTEL_IVB_EX, "MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD"},
    {INTEL_IVB_EX, "MEM_TRANS_RETIRED:PRECISE_STORE"},

    {INTEL_ICL, "MEM_TRANS_RETIRED:LOAD_LATENCY:ldlat=3"},
    {INTEL_ICL, "MEM_INST_RETIRED:ALL_STORES"},

    {INTEL_SKX, "MEM_TRANS_RETIRED:LOAD_LATENCY:ldlat=3"},
    {INTEL_SKX, "MEM_UOPS_RETIRED:ALL_STORES"},

    {INTEL_BDX, "MEM_TRANS_RETIRED:LOAD_LATENCY:ldlat=3"},
    {INTEL_BDX, "MEM_UOPS_RETIRED:ALL_STORES"},

    {INTEL_HSX, "MEM_TRANS_RETIRED:LOAD_LATENCY:ldlat=3"},
    {INTEL_HSX, "MEM_UOPS_RETIRED:ALL_STORES"},

    {INTEL_NHM_EX, "MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD:ldlat=3"},

    {INTEL_WSM_EX, "MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD:ldlat=3"},

    {INTEL_KNL, "OFFCORE_RESPONSE_0"} //,    {INTEL_KNL, "MEM_UOPS_RETIRED:L2_MISS_LOAD"}
};

#endif // __PMU_X86_H__