HPCToolkit
pmu_x86.h
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46 
47 
48 #ifndef __PMU_X86_H__
49 #define __PMU_X86_H__
50 
51 #include <utilities/arch/cpuid.h>
52 
53 struct pmu_config_s {
55  const char *event;
56 };
57 
64  {INTEL_SNB, "MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD"},
65  {INTEL_SNB, "MEM_TRANS_RETIRED:PRECISE_STORE"},
66 
67  {INTEL_SNB_EP, "MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD"},
68  {INTEL_SNB_EP, "MEM_TRANS_RETIRED:PRECISE_STORE"},
69 
70  {INTEL_IVB_EX, "MEM_TRANS_RETIRED:LATENCY_ABOVE_THRESHOLD"},
71  {INTEL_IVB_EX, "MEM_TRANS_RETIRED:PRECISE_STORE"},
72 
73  {INTEL_ICL, "MEM_TRANS_RETIRED:LOAD_LATENCY:ldlat=3"},
74  {INTEL_ICL, "MEM_INST_RETIRED:ALL_STORES"},
75 
76  {INTEL_SKX, "MEM_TRANS_RETIRED:LOAD_LATENCY:ldlat=3"},
77  {INTEL_SKX, "MEM_UOPS_RETIRED:ALL_STORES"},
78 
79  {INTEL_BDX, "MEM_TRANS_RETIRED:LOAD_LATENCY:ldlat=3"},
80  {INTEL_BDX, "MEM_UOPS_RETIRED:ALL_STORES"},
81 
82  {INTEL_HSX, "MEM_TRANS_RETIRED:LOAD_LATENCY:ldlat=3"},
83  {INTEL_HSX, "MEM_UOPS_RETIRED:ALL_STORES"},
84 
85  {INTEL_NHM_EX, "MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD:ldlat=3"},
86 
87  {INTEL_WSM_EX, "MEM_INST_RETIRED:LATENCY_ABOVE_THRESHOLD:ldlat=3"},
88 
90  {INTEL_KNL, "OFFCORE_RESPONSE_0"} //, {INTEL_KNL, "MEM_UOPS_RETIRED:L2_MISS_LOAD"}
91 };
92 
93 #endif // __PMU_X86_H__
const char * event
Definition: pmu_x86.h:55
cpu_type_t cpu
Definition: pmu_x86.h:54
cpu_type_t
Definition: cpuid.h:62
struct pmu_config_s pmu_events[]
Definition: pmu_x86.h:63