HPCToolkit
instruction-set.h
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47 //***************************************************************************
48 //
49 // File:
50 // $HeadURL$
51 //
52 // Purpose:
53 // PPC64 ISA
54 //
55 // Description:
56 // [The set of functions, macros, etc. defined in the file]
57 //
58 // Author:
59 // []
60 //
61 //***************************************************************************
62 
63 #ifndef isa_instructionset_ppc_h
64 #define isa_instructionset_ppc_h
65 
66 #include <inttypes.h>
67 
68 //****************************************************************************
69 //
70 //****************************************************************************
71 
72 //***************************************************************************
73 // Registers
74 //***************************************************************************
75 
76 #define PPC_REG_R0 0
77 #define PPC_REG_RA PPC_REG_R0 /* typical, but not always */
78 
79 #define PPC_REG_R1 1
80 #define PPC_REG_SP PPC_REG_R1 /* apparently R1 is always SP */
81 #define PPC_REG_FP PPC_REG_R1 /* apparently never */
82 
83 #define PPC_REG_R2 2
84 /* ... */
85 #define PPC_REG_R31 31
86 
87 #define PPC_REG_PC 32
88 
89 #define PPC_REG_LR (-1)
90 
91 
92 //***************************************************************************
93 // Operands
94 //***************************************************************************
95 
96 #define PPC_OPND_REG_S_MASK 0x03e00000
97 #define PPC_OPND_REG_S_SHIFT 21
98 #define PPC_OPND_REG_S(insn) \
99  (((insn) & PPC_OPND_REG_S_MASK) >> PPC_OPND_REG_S_SHIFT)
100 
101 #define PPC_OPND_REG_T_MASK PPC_OPND_REG_S_MASK
102 #define PPC_OPND_REG_T_SHIFT PPC_OPND_REG_S_SHIFT
103 #define PPC_OPND_REG_T(insn) PPC_OPND_REG_S(insn)
104 
105 #define PPC_OPND_REG_A_MASK 0x001f0000
106 #define PPC_OPND_REG_A_SHIFT 16
107 #define PPC_OPND_REG_A(insn) \
108  (((insn) & PPC_OPND_REG_A_MASK) >> PPC_OPND_REG_A_SHIFT)
109 
110 #define PPC_OPND_REG_B_MASK 0x0000f800
111 #define PPC_OPND_REG_B_SHIFT 11
112 #define PPC_OPND_REG_B(insn) \
113  (((insn) & PPC_OPND_REG_B_MASK) >> PPC_OPND_REG_B_SHIFT)
114 
115 #define PPC_OPND_CC_MASK 0x00000001 /* Condition code bit */
116 #define PPC_OPND_CC_SHIFT 0
117 
118 #define PPC_OPND_REG_SPR_MASK (PPC_OPND_REG_A_MASK | PPC_OPND_REG_B_MASK)
119 #define PPC_OPND_REG_SPR_SHIFT 16
120 #define PPC_OPND_REG_SPR(insn) \
121  (((insn) & PPC_OPND_REG_SPR_MASK) >> PPC_OPND_REG_SPR_SHIFT)
122 
123 
124 #define PPC_OPND_DISP(x) (((int16_t)((x) & 0x0000ffff)))
125 #define PPC_OPND_DISP_DS(x) (((int16_t)((x) & 0x0000fffc)))
126 
127 
128 //***************************************************************************
129 // Opcodes
130 //***************************************************************************
131 
132 #define PPC_OP_D_MASK 0xfc000000 /* opcode */
133 #define PPC_OP_DS_MASK 0xfc000003 /* opcode, extra-opc */
134 #define PPC_OP_I_MASK 0xfc000003 /* opcode, AA, LK */
135 #define PPC_OP_X_MASK 0xfc0007fe /* opcode, extra-opc */
136 #define PPC_OP_XFX_MASK 0xfc0007fe /* opcode, extra-opc */
137 #define PPC_OP_XFX_SPR_MASK (PPC_OP_XFX_MASK | PPC_OPND_REG_SPR_MASK)
138 
139 #define PPC_OP_LWZ 0x80000000 /* D-form */
140 
141 #define PPC_OP_STW 0x90000000 /* D-form */
142 #define PPC_OP_STD 0xf8000000 /* DS-form */
143 
144 #define PPC_OP_STWU 0x94000000 /* D-form */
145 #define PPC_OP_STDU 0xf8000001 /* DS-form */
146 
147 #define PPC_OP_ADDI 0x38000000 /* D-form */
148 #define PPC_OP_ADDIS 0x3c000000 /* D-form */
149 #define PPC_OP_LIS PPC_OP_ADDIS /* D-form: lis Rx,v = addis Rx,0,v */
150 
151 #define PPC_OP_STWUX 0x7c00016e /* X-form */
152 #define PPC_OP_STDUX 0x7c00016a /* X-form */
153 
154 #define PPC_OP_OR 0x7c000378 /* X-form */
155 #define PPC_OP_MR PPC_OP_OR /* X-form: mr Rx Ry = or Rx Ry Ry */
156 
157 #define PPC_OP_BLR 0x4e800020 /* XL-form */
158 #define PPC_OP_BL 0x48000001 /* I-form */
159 
160 #define PPC_OP_MFSPR 0x7c0002a6 /* XFX-form (2 args) */
161 #define PPC_OP_MFLR 0x7c0802a6 /* XFX-form (1 arg) */
162 
163 #define PPC_OP_MTSPR 0x7c0003a6 /* XFX-form (2 args) */
164 #define PPC_OP_MTLR 0x7c0803a6 /* XFX-form (1 arg) */
165 
166 
167 
168 //***************************************************************************
169 // Instructions
170 //***************************************************************************
171 
172 #define PPC_INSN_D_MASK 0xffff0000 /* opcode RS, RA */
173 #define PPC_INSN_DS_MASK 0xffff0003 /* opcode RS, RA , extra-opc */
174 #define PPC_INSN_X_MASK 0xfffffffe /* opcode RS, RA, RB, extra-opc */
175 #define PPC_INSN_XFX_MASK 0xfffffffe /* opcode RS, SPR, extra-opc */
176 
177 #define PPC_INSN_D(opc, RS, RA, D) \
178  ((opc) | ((RS) << PPC_OPND_REG_S_SHIFT) \
179  | ((RA) << PPC_OPND_REG_A_SHIFT) \
180  | (D))
181 
182 #define PPC_INSN_DS(opc, RS, RA, D) \
183  ((opc) | ((RS) << PPC_OPND_REG_S_SHIFT) \
184  | ((RA) << PPC_OPND_REG_A_SHIFT) \
185  | ((D) << 2))
186 
187 #define PPC_INSN_X(opc, RS, RA, RB, Rc) \
188  ((opc) | ((RS) << PPC_OPND_REG_S_SHIFT) \
189  | ((RA) << PPC_OPND_REG_A_SHIFT) \
190  | ((RB) << PPC_OPND_REG_B_SHIFT) \
191  | (Rc))
192 
193 #define PPC_INSN_XFX1(opc, RS) \
194  ((opc) | ((RS) << PPC_OPND_REG_S_SHIFT))
195 
196 #define PPC_INSN_XFX2(opc, RS, SPR) \
197  ((opc) | ((RS) << PPC_OPND_REG_S_SHIFT) \
198  | ((SPR) << PPC_OPND_REG_SPR_SHIFT))
199 
200 /****************************************************************************/
201 
202 #endif /* isa_instructionset_ppc_h */