HPCToolkit
instruction-set.h
Go to the documentation of this file.
1 // -*-Mode: C++;-*- // technically C99
2 
3 // * BeginRiceCopyright *****************************************************
4 //
5 // $HeadURL$
6 // $Id$
7 //
8 // --------------------------------------------------------------------------
9 // Part of HPCToolkit (hpctoolkit.org)
10 //
11 // Information about sources of support for research and development of
12 // HPCToolkit is at 'hpctoolkit.org' and in 'README.Acknowledgments'.
13 // --------------------------------------------------------------------------
14 //
15 // Copyright ((c)) 2002-2019, Rice University
16 // All rights reserved.
17 //
18 // Redistribution and use in source and binary forms, with or without
19 // modification, are permitted provided that the following conditions are
20 // met:
21 //
22 // * Redistributions of source code must retain the above copyright
23 // notice, this list of conditions and the following disclaimer.
24 //
25 // * Redistributions in binary form must reproduce the above copyright
26 // notice, this list of conditions and the following disclaimer in the
27 // documentation and/or other materials provided with the distribution.
28 //
29 // * Neither the name of Rice University (RICE) nor the names of its
30 // contributors may be used to endorse or promote products derived from
31 // this software without specific prior written permission.
32 //
33 // This software is provided by RICE and contributors "as is" and any
34 // express or implied warranties, including, but not limited to, the
35 // implied warranties of merchantability and fitness for a particular
36 // purpose are disclaimed. In no event shall RICE or contributors be
37 // liable for any direct, indirect, incidental, special, exemplary, or
38 // consequential damages (including, but not limited to, procurement of
39 // substitute goods or services; loss of use, data, or profits; or
40 // business interruption) however caused and on any theory of liability,
41 // whether in contract, strict liability, or tort (including negligence
42 // or otherwise) arising in any way out of the use of this software, even
43 // if advised of the possibility of such damage.
44 //
45 // ******************************************************* EndRiceCopyright *
46 
47 //***************************************************************************
48 //
49 // File:
50 // alpha.h
51 //
52 // Purpose:
53 // [The purpose of this file]
54 //
55 // Description:
56 // [The set of functions, macros, etc. defined in the file]
57 //
58 //***************************************************************************
59 
60 #ifndef ALPHA_INSTRUCTIONS_H
61 #define ALPHA_INSTRUCTIONS_H
62 
63 #include "inttypes.h"
64 
65 // Information about Alpha instructions, encoding, conventions, and
66 // section numbers is from
67 // Alpha Architecture Reference Manual, Fourth Edition
68 // (January 2002; (c) Compaq Computer Corporation 2002)
69 // It is available at the following anonymous FTP site:
70 // ftp.compaq.com/pub/products/alphaCPUdocs/alpha_arch_ref.pdf
71 
72 // Some of the opcode definitions have been cross-checked with the
73 // alpha opcode table from GNU's binutils ("opcodes/alpha-opc.c") and
74 // the file '/usr/include/machine/inst.h'.
75 
76 // ==========================================================================
77 
78 // Opcode Classes and Masks
79 
80 // Instruction Formats: See 3.3 Instruction Formats
81 
82 // There are five basic Alpha instruction formats. All instruction
83 // formats are 32 bits long with a 6-bit major opcode field in bits
84 // <31:26> of the instruction.
85 
86 // There are five basic Alpha instruction formats. All instruction formats
87 // are 32 bits long with a 6-bit major opcode field in bits <31:26> of the
88 // instruction. (See 3.3.1 -- 3.3.5, respectively.)
89 // 31 ......................................................... 0
90 // Memory: opcode(6), Ra(5), Rb(5), Memory_displacemnt(16)
91 // (note 1)
92 // Branch: opcode(6), Ra(5), Branch_displacment(21)
93 // (note 2)
94 // Operate: opcode(6), Ra(5), Rb(5), SBz(3), LitBit(1), Function(7), Rc(5)
95 // opcode(6), Ra(5), Literal(8), LitBit(1), Function(7), Rc(5)
96 // FP Operate: opcode(6), Fa(5), Fb(5), Function(11), Fc(5)
97 // PALcode: opcode(6), PALcode function(26)
98 //
99 // Note 1: The displacement field is a byte offset. It is
100 // sign-extended and added to the contents of register Rb to form a
101 // virtual address. Overflow is ignored in this calculation.
102 //
103 // Note 2: The displacement is treated as a longword offset. This
104 // means it is shifted left two bits (to address a longword boundary),
105 // sign-extended to 64 bits, and added to the updated PC to form the
106 // target virtual address. Overflow is ignored in this
107 // calculation. The target virtual address (va) is computed as
108 // follows: va <-- PC + {4*SEXT(Branch_disp)}
109 
110 // ==========================================================================
111 
112 // Macros for forming the opcodes and Masks for decoding instructions.
113 // The mask places a 1-bit at every location used to decode an
114 // instruction. AND the mask with the instruction to find the opcode.
115 
116 // See Appendix C (of the "Alpha Architecture Handbook" referenced
117 // above) and esp. section C.1 and tables C-1, C-2 for the template
118 // behind this encoding scheme.
119 
120 // The main opcode
121 #define OP(x) (uint32_t)(((x) & 0x3F) << 26)
122 #define OP_MASK 0xFC000000 /* opcode: bits 31-26 */
123 
124 // =========================================
125 
126 // Memory format instructions (3.3.1)
127 #define MEM(oo) OP(oo)
128 #define MEM_MASK OP_MASK
129 
130 // Memory/Func Code format instructions (3.3.1.1)
131 #define MFC(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF))
132 #define MFC_MASK (OP_MASK | 0xFFFF) /* opcode + function bits 15-0 */
133 
134 // Memory/Branch format instructions (3.3.1.2 and 4.3.3)
135 #define MBR(oo,h) (OP(oo) | (((h) & 0x3) << 14))
136 #define MBR_MASK (OP_MASK | 0xC000) /* opcode + hint bits 15-14 */
137 
138 // =========================================
139 
140 // Branch format instructions (3.3.2)
141 #define BRA(oo) OP(oo)
142 #define BRA_MASK OP_MASK
143 
144 // =========================================
145 
146 // Operate format instructions. The OPRL variant specifies a
147 // literal second argument.
148 #define OPR(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5))
149 #define OPRL(oo,ff) (OPR((oo),(ff)) | 0x1000)
150 #define OPR_MASK (OP_MASK | 0x1FE0) /* opcode + litbit 12 +
151  function bits 11-5 */
152 
153 // =========================================
154 
155 // Floating point format instructions
156 #define FP(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5))
157 #define FP_MASK (OP_MASK | 0xFFE0) /* opcode + function bits 15-5 */
158 
159 // =========================================
160 
161 // Generic PALcode format instructions
162 #define PCD(oo) OP(oo)
163 #define PCD_MASK OP_MASK
164 
165 // Specific PALcode instructions
166 #define SPCD(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF))
167 #define SPCD_MASK 0xFFFFFFFF /* opcode + function bits 25-0 */
168 
169 // Hardware memory (hw_{ld,st}) instructions (D.1) (use PAL macros)
170 
171 // =========================================
172 
173 // Some useful opcode values for instruction classes
174 
175 // Use the `Operate format' mask for the following
176 #define OpIntArith OP(0x10) /* Integer arithmetic instruction opcodes */
177 #define OpIntLogic OP(0x11) /* Integer logical instruction opcodes */
178 #define OpIntShift OP(0x12) /* Integer shift instruction opcodes */
179 #define OpIntMult OP(0x13) /* Integer multiply instruction opcodes */
180 
181 // Use the `FP operate' mask for the following
182 #define OpIntToFlt OP(0x14) /* Integer to FP register move opcodes */
183 #define OpFltVAX OP(0x15) /* VAX floating-point instruction opcodes */
184 #define OpFltIEEE OP(0x16) /* IEEE floating-point instruction opcodes */
185 #define OpFltOp OP(0x17) /* Floating-point Operate instruction opcodes */
186 
187 // Use the `Memory/Func Code' mask
188 #define OpMisc OP(0x18) /* Miscellaneous instruction opcodes */
189 
190 // Use the `FP operate' mask (but note there are both OPR and FP instructions)
191 #define OpFltToInt OP(0x1C) /* FP to integer register move opcodes */
192 
193 // Use the `Memory/Branch format' mask
194 #define OpJump OP(0x1A) /* Jump instruction opcodes */
195 
196 // ==========================================================================
197 
198 // Memory Integer/FP Load/Store Instructions (SS 4.2 and 4.8; Tables
199 // 4-2 and 4-14)
200 
201 // Memory format instructions
202 
203 #define LDA MEM(0x08)
204 #define LDAH MEM(0x09)
205 #define LDBU MEM(0x0A)
206 #define UNOP MEM(0x0B) /*pseudo*/
207 #define LDQ_U MEM(0x0B)
208 #define LDWU MEM(0x0C)
209 #define STW MEM(0x0D)
210 #define STB MEM(0x0E)
211 #define STQ_U MEM(0x0F)
212 
213 #define LDF MEM(0x20)
214 #define LDG MEM(0x21)
215 #define LDS MEM(0x22)
216 #define LDT MEM(0x23)
217 #define STF MEM(0x24)
218 #define STG MEM(0x25)
219 #define STS MEM(0x26)
220 #define STT MEM(0x27)
221 
222 #define LDL MEM(0x28)
223 #define LDQ MEM(0x29)
224 #define LDL_L MEM(0x2A)
225 #define LDQ_L MEM(0x2B)
226 #define STL MEM(0x2C)
227 #define STQ MEM(0x2D)
228 #define STL_C MEM(0x2E)
229 #define STQ_C MEM(0x2F)
230 
231 // =========================================
232 
233 // Miscellaneous Instructions (SS 4.11, Table 4-17)
234 // [except AMASK, CALL_PAL, IMPLVER]
235 // VAX compatibility Instructions (SS 4.12, Table 4-18)
236 
237 // Memory/Func Code format instructions
238 
239 #define TRAPB MFC(0x18,0x0000)
240 #define DRAINT MFC(0x18,0x0000) /*alias*/
241 #define EXCB MFC(0x18,0x0400)
242 #define MB MFC(0x18,0x4000)
243 #define WMB MFC(0x18,0x4400)
244 #define FETCH MFC(0x18,0x8000)
245 #define FETCH_M MFC(0x18,0xA000)
246 #define RPCC MFC(0x18,0xC000)
247 #define RC MFC(0x18,0xE000)
248 #define ECB MFC(0x18,0xE800)
249 #define RS MFC(0x18,0xF000)
250 #define WH64 MFC(0x18,0xF800)
251 
252 // =========================================
253 
254 // Integer/FP control Instructions (SS 4.3 and 4.9; Tables 4-3
255 // and 4-15)
256 
257 // Memory/Branch format instructions
258 
259 #define JMP MBR(0x1A,0)
260 #define JSR MBR(0x1A,1)
261 #define RET MBR(0x1A,2)
262 #define JCR MBR(0x1A,3) /*alias*/
263 #define JSR_COROUTINE MBR(0x1A,3)
264 
265 // Branch format instructions
266 
267 #define BR BRA(0x30)
268 #define FBEQ BRA(0x31)
269 #define FBLT BRA(0x32)
270 #define FBLE BRA(0x33)
271 #define BSR BRA(0x34)
272 #define FBNE BRA(0x35)
273 #define FBGE BRA(0x36)
274 #define FBGT BRA(0x37)
275 #define BLBC BRA(0x38)
276 #define BEQ BRA(0x39)
277 #define BLT BRA(0x3A)
278 #define BLE BRA(0x3B)
279 #define BLBS BRA(0x3C)
280 #define BNE BRA(0x3D)
281 #define BGE BRA(0x3E)
282 #define BGT BRA(0x3F)
283 
284 // =========================================
285 
286 // Integer/FP operate Instructions (SS 4.4, 4.5, 4.6 and 4.10; Tables 4-5,
287 // 4-7, 4-7, 4-16)
288 
289 // Operate format instructions. (The literal version of each of these
290 // instructions can be formed by substituting `OPRL' for `OPR'. This
291 // sets the literal bit.)
292 
293 // (Mostly) SS 4.4, Table 4-5: Integer Arithmetic
294 
295 #define SEXTL OPR(0x10,0x00) /*pseudo*/
296 #define ADDL OPR(0x10,0x00)
297 #define S4ADDL OPR(0x10,0x02)
298 #define NEGL OPR(0x10,0x09) /*pseudo*/
299 #define SUBL OPR(0x10,0x09)
300 #define S4SUBL OPR(0x10,0x0B)
301 #define CMPBGE OPR(0x10,0x0F)
302 #define S8ADDL OPR(0x10,0x12)
303 #define S8SUBL OPR(0x10,0x1B)
304 #define CMPULT OPR(0x10,0x1D)
305 #define ADDQ OPR(0x10,0x20)
306 #define S4ADDQ OPR(0x10,0x22)
307 #define NEGQ OPR(0x10,0x29) /*pseudo*/
308 #define SUBQ OPR(0x10,0x29)
309 #define S4SUBQ OPR(0x10,0x2B)
310 #define CMPEQ OPR(0x10,0x2D)
311 #define S8ADDQ OPR(0x10,0x32)
312 #define S8SUBQ OPR(0x10,0x3B)
313 #define CMPULE OPR(0x10,0x3D)
314 #define ADDL_V OPR(0x10,0x40)
315 #define NEGL_V OPR(0x10,0x49) /*pseudo*/
316 #define SUBL_V OPR(0x10,0x49)
317 #define CMPLT OPR(0x10,0x4D)
318 #define ADDQ_V OPR(0x10,0x60)
319 #define NEGQ_V OPR(0x10,0x69) /*pseudo*/
320 #define SUBQ_V OPR(0x10,0x69)
321 #define CMPLE OPR(0x10,0x6D)
322 
323 // (Mostly) SS 4.5, Table 4-6: Logical and Shift Instructions
324 #undef AND
325 #define AND OPR(0x11,0x00)
326 #define ANDNOT OPR(0x11,0x08) /*alias*/
327 #define BIC OPR(0x11,0x08)
328 #define CMOVLBS OPR(0x11,0x14)
329 #define CMOVLBC OPR(0x11,0x16)
330 #define NOP OPR(0x11,0x20) /* int nop (see unop) */ /*pseudo*/
331 #define CLR OPR(0x11,0x20) /*pseudo*/
332 #define MOV OPR(0x11,0x20) /*pseudo*/
333 #define OR OPR(0x11,0x20) /*alias*/
334 #define BIS OPR(0x11,0x20)
335 #define CMOVEQ OPR(0x11,0x24)
336 #define CMOVNE OPR(0x11,0x26)
337 #undef NOT
338 #define NOT OPR(0x11,0x28) /*pseudo*/
339 #define ORNOT OPR(0x11,0x28)
340 #define XOR OPR(0x11,0x40)
341 #define CMOVLT OPR(0x11,0x44)
342 #define CMOVGE OPR(0x11,0x46)
343 #define EQV OPR(0x11,0x48)
344 #define XORNOT OPR(0x11,0x48) /*alias*/
345 #define AMASK OPR(0x11,0x61)
346 #define CMOVLE OPR(0x11,0x64)
347 #define CMOVGT OPR(0x11,0x66)
348 #define IMPLVER OPRL(0x11,0x6C)|(31<<21)|(1<<13)
349 
350 // (Mostly) SS 4.6, Table 4-7: Byte Manipulation Instructions
351 #define MSKBL OPR(0x12,0x02)
352 #define EXTBL OPR(0x12,0x06)
353 #define INSBL OPR(0x12,0x0B)
354 #define MSKWL OPR(0x12,0x12)
355 #define EXTWL OPR(0x12,0x16)
356 #define INSWL OPR(0x12,0x1B)
357 #define MSKLL OPR(0x12,0x22)
358 #define EXTLL OPR(0x12,0x26)
359 #define INSLL OPR(0x12,0x2B)
360 #define ZAP OPR(0x12,0x30)
361 #define ZAPNOT OPR(0x12,0x31)
362 #define MSKQL OPR(0x12,0x32)
363 #define SRL OPR(0x12,0x34)
364 #define EXTQL OPR(0x12,0x36)
365 #define SLL OPR(0x12,0x39)
366 #define INSQL OPR(0x12,0x3B)
367 #define SRA OPR(0x12,0x3C)
368 #define MSKWH OPR(0x12,0x52)
369 #define INSWH OPR(0x12,0x57)
370 #define EXTWH OPR(0x12,0x5A)
371 #define MSKLH OPR(0x12,0x62)
372 #define INSLH OPR(0x12,0x67)
373 #define EXTLH OPR(0x12,0x6A)
374 #define MSKQH OPR(0x12,0x72)
375 #define INSQH OPR(0x12,0x77)
376 #define EXTQH OPR(0x12,0x7A)
377 
378 #define MULL OPR(0x13,0x00)
379 #define MULQ OPR(0x13,0x20)
380 #define UMULH OPR(0x13,0x30)
381 #define MULL_V OPR(0x13,0x40)
382 #define MULQ_V OPR(0x13,0x60)
383 
384 #define SEXTB OPR(0x1C, 0x00)
385 #define SEXTW OPR(0x1C, 0x01)
386 #define CTPOP OPR(0x1C, 0x30)
387 #define CTLZ OPR(0x1C, 0x32)
388 #define CTTZ OPR(0x1C, 0x33)
389 
390 // =========================================
391 
392 // SS 4.10, Table 4-16: Floating-Point Operate
393 
394 // Floating point format instructions
395 
396 #define ITOFS FP(0x14,0x004)
397 #define SQRTF_C FP(0x14,0x00A)
398 #define SQRTS_C FP(0x14,0x00B)
399 #define ITOFF FP(0x14,0x014)
400 #define ITOFT FP(0x14,0x024)
401 #define SQRTG_C FP(0x14,0x02A)
402 #define SQRTT_C FP(0x14,0x02B)
403 #define SQRTS_M FP(0x14,0x04B)
404 #define SQRTT_M FP(0x14,0x06B)
405 #define SQRTF FP(0x14,0x08A)
406 #define SQRTS FP(0x14,0x08B)
407 #define SQRTG FP(0x14,0x0AA)
408 #define SQRTT FP(0x14,0x0AB)
409 #define SQRTS_D FP(0x14,0x0CB)
410 #define SQRTT_D FP(0x14,0x0EB)
411 #define SQRTF_UC FP(0x14,0x10A)
412 #define SQRTS_UC FP(0x14,0x10B)
413 #define SQRTG_UC FP(0x14,0x12A)
414 #define SQRTT_UC FP(0x14,0x12B)
415 #define SQRTS_UM FP(0x14,0x14B)
416 #define SQRTT_UM FP(0x14,0x16B)
417 #define SQRTF_U FP(0x14,0x18A)
418 #define SQRTS_U FP(0x14,0x18B)
419 #define SQRTG_U FP(0x14,0x1AA)
420 #define SQRTT_U FP(0x14,0x1AB)
421 #define SQRTS_UD FP(0x14,0x1CB)
422 #define SQRTT_UD FP(0x14,0x1EB)
423 #define SQRTF_SC FP(0x14,0x40A)
424 #define SQRTG_SC FP(0x14,0x42A)
425 #define SQRTF_S FP(0x14,0x48A)
426 #define SQRTG_S FP(0x14,0x4AA)
427 #define SQRTF_SUC FP(0x14,0x50A)
428 #define SQRTS_SUC FP(0x14,0x50B)
429 #define SQRTG_SUC FP(0x14,0x52A)
430 #define SQRTT_SUC FP(0x14,0x52B)
431 #define SQRTS_SUM FP(0x14,0x54B)
432 #define SQRTT_SUM FP(0x14,0x56B)
433 #define SQRTF_SU FP(0x14,0x58A)
434 #define SQRTS_SU FP(0x14,0x58B)
435 #define SQRTG_SU FP(0x14,0x5AA)
436 #define SQRTT_SU FP(0x14,0x5AB)
437 #define SQRTS_SUD FP(0x14,0x5CB)
438 #define SQRTT_SUD FP(0x14,0x5EB)
439 #define SQRTS_SUIC FP(0x14,0x70B)
440 #define SQRTT_SUIC FP(0x14,0x72B)
441 #define SQRTS_SUIM FP(0x14,0x74B)
442 #define SQRTT_SUIM FP(0x14,0x76B)
443 #define SQRTS_SUI FP(0x14,0x78B)
444 #define SQRTT_SUI FP(0x14,0x7AB)
445 #define SQRTS_SUID FP(0x14,0x7CB)
446 #define SQRTT_SUID FP(0x14,0x7EB)
447 
448 #define ADDF_C FP(0x15,0x000)
449 #define SUBF_C FP(0x15,0x001)
450 #define MULF_C FP(0x15,0x002)
451 #define DIVF_C FP(0x15,0x003)
452 #define CVTDG_C FP(0x15,0x01E)
453 #define ADDG_C FP(0x15,0x020)
454 #define SUBG_C FP(0x15,0x021)
455 #define MULG_C FP(0x15,0x022)
456 #define DIVG_C FP(0x15,0x023)
457 #define CVTGF_C FP(0x15,0x02C)
458 #define CVTGD_C FP(0x15,0x02D)
459 #define CVTGQ_C FP(0x15,0x02F)
460 #define CVTQF_C FP(0x15,0x03C)
461 #define CVTQG_C FP(0x15,0x03E)
462 #define ADDF FP(0x15,0x080)
463 #define NEGF FP(0x15,0x081) /*pseudo*/
464 #define SUBF FP(0x15,0x081)
465 #define MULF FP(0x15,0x082)
466 #define DIVF FP(0x15,0x083)
467 #define CVTDG FP(0x15,0x09E)
468 #define ADDG FP(0x15,0x0A0)
469 #define NEGG FP(0x15,0x0A1) /*pseudo*/
470 #define SUBG FP(0x15,0x0A1)
471 #define MULG FP(0x15,0x0A2)
472 #define DIVG FP(0x15,0x0A3)
473 #define CMPGEQ FP(0x15,0x0A5)
474 #define CMPGLT FP(0x15,0x0A6)
475 #define CMPGLE FP(0x15,0x0A7)
476 #define CVTGF FP(0x15,0x0AC)
477 #define CVTGD FP(0x15,0x0AD)
478 #define CVTGQ FP(0x15,0x0AF)
479 #define CVTQF FP(0x15,0x0BC)
480 #define CVTQG FP(0x15,0x0BE)
481 #define ADDF_UC FP(0x15,0x100)
482 #define SUBF_UC FP(0x15,0x101)
483 #define MULF_UC FP(0x15,0x102)
484 #define DIVF_UC FP(0x15,0x103)
485 #define CVTDG_UC FP(0x15,0x11E)
486 #define ADDG_UC FP(0x15,0x120)
487 #define SUBG_UC FP(0x15,0x121)
488 #define MULG_UC FP(0x15,0x122)
489 #define DIVG_UC FP(0x15,0x123)
490 #define CVTGF_UC FP(0x15,0x12C)
491 #define CVTGD_UC FP(0x15,0x12D)
492 #define CVTGQ_VC FP(0x15,0x12F)
493 #define ADDF_U FP(0x15,0x180)
494 #define SUBF_U FP(0x15,0x181)
495 #define MULF_U FP(0x15,0x182)
496 #define DIVF_U FP(0x15,0x183)
497 #define CVTDG_U FP(0x15,0x19E)
498 #define ADDG_U FP(0x15,0x1A0)
499 #define SUBG_U FP(0x15,0x1A1)
500 #define MULG_U FP(0x15,0x1A2)
501 #define DIVG_U FP(0x15,0x1A3)
502 #define CVTGF_U FP(0x15,0x1AC)
503 #define CVTGD_U FP(0x15,0x1AD)
504 #define CVTGQ_V FP(0x15,0x1AF)
505 #define ADDF_SC FP(0x15,0x400)
506 #define SUBF_SC FP(0x15,0x401)
507 #define MULF_SC FP(0x15,0x402)
508 #define DIVF_SC FP(0x15,0x403)
509 #define CVTDG_SC FP(0x15,0x41E)
510 #define ADDG_SC FP(0x15,0x420)
511 #define SUBG_SC FP(0x15,0x421)
512 #define MULG_SC FP(0x15,0x422)
513 #define DIVG_SC FP(0x15,0x423)
514 #define CVTGF_SC FP(0x15,0x42C)
515 #define CVTGD_SC FP(0x15,0x42D)
516 #define CVTGQ_SC FP(0x15,0x42F)
517 #define ADDF_S FP(0x15,0x480)
518 #define NEGF_S FP(0x15,0x481) /*pseudo*/
519 #define SUBF_S FP(0x15,0x481)
520 #define MULF_S FP(0x15,0x482)
521 #define DIVF_S FP(0x15,0x483)
522 #define CVTDG_S FP(0x15,0x49E)
523 #define ADDG_S FP(0x15,0x4A0)
524 #define NEGG_S FP(0x15,0x4A1) /*pseudo*/
525 #define SUBG_S FP(0x15,0x4A1)
526 #define MULG_S FP(0x15,0x4A2)
527 #define DIVG_S FP(0x15,0x4A3)
528 #define CMPGEQ_S FP(0x15,0x4A5)
529 #define CMPGLT_S FP(0x15,0x4A6)
530 #define CMPGLE_S FP(0x15,0x4A7)
531 #define CVTGF_S FP(0x15,0x4AC)
532 #define CVTGD_S FP(0x15,0x4AD)
533 #define CVTGQ_S FP(0x15,0x4AF)
534 #define ADDF_SUC FP(0x15,0x500)
535 #define SUBF_SUC FP(0x15,0x501)
536 #define MULF_SUC FP(0x15,0x502)
537 #define DIVF_SUC FP(0x15,0x503)
538 #define CVTDG_SUC FP(0x15,0x51E)
539 #define ADDG_SUC FP(0x15,0x520)
540 #define SUBG_SUC FP(0x15,0x521)
541 #define MULG_SUC FP(0x15,0x522)
542 #define DIVG_SUC FP(0x15,0x523)
543 #define CVTGF_SUC FP(0x15,0x52C)
544 #define CVTGD_SUC FP(0x15,0x52D)
545 #define CVTGQ_SVC FP(0x15,0x52F)
546 #define ADDF_SU FP(0x15,0x580)
547 #define SUBF_SU FP(0x15,0x581)
548 #define MULF_SU FP(0x15,0x582)
549 #define DIVF_SU FP(0x15,0x583)
550 #define CVTDG_SU FP(0x15,0x59E)
551 #define ADDG_SU FP(0x15,0x5A0)
552 #define SUBG_SU FP(0x15,0x5A1)
553 #define MULG_SU FP(0x15,0x5A2)
554 #define DIVG_SU FP(0x15,0x5A3)
555 #define CVTGF_SU FP(0x15,0x5AC)
556 #define CVTGD_SU FP(0x15,0x5AD)
557 #define CVTGQ_SV FP(0x15,0x5AF)
558 
559 #define ADDS_C FP(0x16,0x000)
560 #define SUBS_C FP(0x16,0x001)
561 #define MULS_C FP(0x16,0x002)
562 #define DIVS_C FP(0x16,0x003)
563 #define ADDT_C FP(0x16,0x020)
564 #define SUBT_C FP(0x16,0x021)
565 #define MULT_C FP(0x16,0x022)
566 #define DIVT_C FP(0x16,0x023)
567 #define CVTTS_C FP(0x16,0x02C)
568 #define CVTTQ_C FP(0x16,0x02F)
569 #define CVTQS_C FP(0x16,0x03C)
570 #define CVTQT_C FP(0x16,0x03E)
571 #define ADDS_M FP(0x16,0x040)
572 #define SUBS_M FP(0x16,0x041)
573 #define MULS_M FP(0x16,0x042)
574 #define DIVS_M FP(0x16,0x043)
575 #define ADDT_M FP(0x16,0x060)
576 #define SUBT_M FP(0x16,0x061)
577 #define MULT_M FP(0x16,0x062)
578 #define DIVT_M FP(0x16,0x063)
579 #define CVTTS_M FP(0x16,0x06C)
580 #define CVTTQ_M FP(0x16,0x06F)
581 #define CVTQS_M FP(0x16,0x07C)
582 #define CVTQT_M FP(0x16,0x07E)
583 #define ADDS FP(0x16,0x080)
584 #define NEGS FP(0x16,0x081) /*pseudo*/
585 #define SUBS FP(0x16,0x081)
586 #define MULS FP(0x16,0x082)
587 #define DIVS FP(0x16,0x083)
588 #define ADDT FP(0x16,0x0A0)
589 #define NEGT FP(0x16,0x0A1) /*pseudo*/
590 #define SUBT FP(0x16,0x0A1)
591 #define MULT FP(0x16,0x0A2)
592 #define DIVT FP(0x16,0x0A3)
593 #define CMPTUN FP(0x16,0x0A4)
594 #define CMPTEQ FP(0x16,0x0A5)
595 #define CMPTLT FP(0x16,0x0A6)
596 #define CMPTLE FP(0x16,0x0A7)
597 #define CVTTS FP(0x16,0x0AC)
598 #define CVTTQ FP(0x16,0x0AF)
599 #define CVTQS FP(0x16,0x0BC)
600 #define CVTQT FP(0x16,0x0BE)
601 #define ADDS_D FP(0x16,0x0C0)
602 #define SUBS_D FP(0x16,0x0C1)
603 #define MULS_D FP(0x16,0x0C2)
604 #define DIVS_D FP(0x16,0x0C3)
605 #define ADDT_D FP(0x16,0x0E0)
606 #define SUBT_D FP(0x16,0x0E1)
607 #define MULT_D FP(0x16,0x0E2)
608 #define DIVT_D FP(0x16,0x0E3)
609 #define CVTTS_D FP(0x16,0x0EC)
610 #define CVTTQ_D FP(0x16,0x0EF)
611 #define CVTQS_D FP(0x16,0x0FC)
612 #define CVTQT_D FP(0x16,0x0FE)
613 #define ADDS_UC FP(0x16,0x100)
614 #define SUBS_UC FP(0x16,0x101)
615 #define MULS_UC FP(0x16,0x102)
616 #define DIVS_UC FP(0x16,0x103)
617 #define ADDT_UC FP(0x16,0x120)
618 #define SUBT_UC FP(0x16,0x121)
619 #define MULT_UC FP(0x16,0x122)
620 #define DIVT_UC FP(0x16,0x123)
621 #define CVTTS_UC FP(0x16,0x12C)
622 #define CVTTQ_VC FP(0x16,0x12F)
623 #define ADDS_UM FP(0x16,0x140)
624 #define SUBS_UM FP(0x16,0x141)
625 #define MULS_UM FP(0x16,0x142)
626 #define DIVS_UM FP(0x16,0x143)
627 #define ADDT_UM FP(0x16,0x160)
628 #define SUBT_UM FP(0x16,0x161)
629 #define MULT_UM FP(0x16,0x162)
630 #define DIVT_UM FP(0x16,0x163)
631 #define CVTTS_UM FP(0x16,0x16C)
632 #define CVTTQ_VM FP(0x16,0x16F)
633 #define ADDS_U FP(0x16,0x180)
634 #define SUBS_U FP(0x16,0x181)
635 #define MULS_U FP(0x16,0x182)
636 #define DIVS_U FP(0x16,0x183)
637 #define ADDT_U FP(0x16,0x1A0)
638 #define SUBT_U FP(0x16,0x1A1)
639 #define MULT_U FP(0x16,0x1A2)
640 #define DIVT_U FP(0x16,0x1A3)
641 #define CVTTS_U FP(0x16,0x1AC)
642 #define CVTTQ_V FP(0x16,0x1AF)
643 #define ADDS_UD FP(0x16,0x1C0)
644 #define SUBS_UD FP(0x16,0x1C1)
645 #define MULS_UD FP(0x16,0x1C2)
646 #define DIVS_UD FP(0x16,0x1C3)
647 #define ADDT_UD FP(0x16,0x1E0)
648 #define SUBT_UD FP(0x16,0x1E1)
649 #define MULT_UD FP(0x16,0x1E2)
650 #define DIVT_UD FP(0x16,0x1E3)
651 #define CVTTS_UD FP(0x16,0x1EC)
652 #define CVTTQ_VD FP(0x16,0x1EF)
653 #define CVTST FP(0x16,0x2AC)
654 #define ADDS_SUC FP(0x16,0x500)
655 #define SUBS_SUC FP(0x16,0x501)
656 #define MULS_SUC FP(0x16,0x502)
657 #define DIVS_SUC FP(0x16,0x503)
658 #define ADDT_SUC FP(0x16,0x520)
659 #define SUBT_SUC FP(0x16,0x521)
660 #define MULT_SUC FP(0x16,0x522)
661 #define DIVT_SUC FP(0x16,0x523)
662 #define CVTTS_SUC FP(0x16,0x52C)
663 #define CVTTQ_SVC FP(0x16,0x52F)
664 #define ADDS_SUM FP(0x16,0x540)
665 #define SUBS_SUM FP(0x16,0x541)
666 #define MULS_SUM FP(0x16,0x542)
667 #define DIVS_SUM FP(0x16,0x543)
668 #define ADDT_SUM FP(0x16,0x560)
669 #define SUBT_SUM FP(0x16,0x561)
670 #define MULT_SUM FP(0x16,0x562)
671 #define DIVT_SUM FP(0x16,0x563)
672 #define CVTTS_SUM FP(0x16,0x56C)
673 #define CVTTQ_SVM FP(0x16,0x56F)
674 #define ADDS_SU FP(0x16,0x580)
675 #define NEGS_SU FP(0x16,0x581) /*pseudo*/
676 #define SUBS_SU FP(0x16,0x581)
677 #define MULS_SU FP(0x16,0x582)
678 #define DIVS_SU FP(0x16,0x583)
679 #define ADDT_SU FP(0x16,0x5A0)
680 #define NEGT_SU FP(0x16,0x5A1) /*pseudo*/
681 #define SUBT_SU FP(0x16,0x5A1)
682 #define MULT_SU FP(0x16,0x5A2)
683 #define DIVT_SU FP(0x16,0x5A3)
684 #define CMPTUN_SU FP(0x16,0x5A4)
685 #define CMPTEQ_SU FP(0x16,0x5A5)
686 #define CMPTLT_SU FP(0x16,0x5A6)
687 #define CMPTLE_SU FP(0x16,0x5A7)
688 #define CVTTS_SU FP(0x16,0x5AC)
689 #define CVTTQ_SV FP(0x16,0x5AF)
690 #define ADDS_SUD FP(0x16,0x5C0)
691 #define SUBS_SUD FP(0x16,0x5C1)
692 #define MULS_SUD FP(0x16,0x5C2)
693 #define DIVS_SUD FP(0x16,0x5C3)
694 #define ADDT_SUD FP(0x16,0x5E0)
695 #define SUBT_SUD FP(0x16,0x5E1)
696 #define MULT_SUD FP(0x16,0x5E2)
697 #define DIVT_SUD FP(0x16,0x5E3)
698 #define CVTTS_SUD FP(0x16,0x5EC)
699 #define CVTTQ_SVD FP(0x16,0x5EF)
700 #define CVTST_S FP(0x16,0x6AC)
701 #define ADDS_SUIC FP(0x16,0x700)
702 #define SUBS_SUIC FP(0x16,0x701)
703 #define MULS_SUIC FP(0x16,0x702)
704 #define DIVS_SUIC FP(0x16,0x703)
705 #define ADDT_SUIC FP(0x16,0x720)
706 #define SUBT_SUIC FP(0x16,0x721)
707 #define MULT_SUIC FP(0x16,0x722)
708 #define DIVT_SUIC FP(0x16,0x723)
709 #define CVTTS_SUIC FP(0x16,0x72C)
710 #define CVTTQ_SVIC FP(0x16,0x72F)
711 #define CVTQS_SUIC FP(0x16,0x73C)
712 #define CVTQT_SUIC FP(0x16,0x73E)
713 #define ADDS_SUIM FP(0x16,0x740)
714 #define SUBS_SUIM FP(0x16,0x741)
715 #define MULS_SUIM FP(0x16,0x742)
716 #define DIVS_SUIM FP(0x16,0x743)
717 #define ADDT_SUIM FP(0x16,0x760)
718 #define SUBT_SUIM FP(0x16,0x761)
719 #define MULT_SUIM FP(0x16,0x762)
720 #define DIVT_SUIM FP(0x16,0x763)
721 #define CVTTS_SUIM FP(0x16,0x76C)
722 #define CVTTQ_SVIM FP(0x16,0x76F)
723 #define CVTQS_SUIM FP(0x16,0x77C)
724 #define CVTQT_SUIM FP(0x16,0x77E)
725 #define ADDS_SUI FP(0x16,0x780)
726 #define NEGS_SUI FP(0x16,0x781) /*pseudo*/
727 #define SUBS_SUI FP(0x16,0x781)
728 #define MULS_SUI FP(0x16,0x782)
729 #define DIVS_SUI FP(0x16,0x783)
730 #define ADDT_SUI FP(0x16,0x7A0)
731 #define NEGT_SUI FP(0x16,0x7A1) /*pseudo*/
732 #define SUBT_SUI FP(0x16,0x7A1)
733 #define MULT_SUI FP(0x16,0x7A2)
734 #define DIVT_SUI FP(0x16,0x7A3)
735 #define CVTTS_SUI FP(0x16,0x7AC)
736 #define CVTTQ_SVI FP(0x16,0x7AF)
737 #define CVTQS_SUI FP(0x16,0x7BC)
738 #define CVTQT_SUI FP(0x16,0x7BE)
739 #define ADDS_SUID FP(0x16,0x7C0)
740 #define SUBS_SUID FP(0x16,0x7C1)
741 #define MULS_SUID FP(0x16,0x7C2)
742 #define DIVS_SUID FP(0x16,0x7C3)
743 #define ADDT_SUID FP(0x16,0x7E0)
744 #define SUBT_SUID FP(0x16,0x7E1)
745 #define MULT_SUID FP(0x16,0x7E2)
746 #define DIVT_SUID FP(0x16,0x7E3)
747 #define CVTTS_SUID FP(0x16,0x7EC)
748 #define CVTTQ_SVID FP(0x16,0x7EF)
749 #define CVTQS_SUID FP(0x16,0x7FC)
750 #define CVTQT_SUID FP(0x16,0x7FE)
751 
752 #define CVTLQ FP(0x17,0x010)
753 #define FNOP FP(0x17,0x020) /*pseudo*/
754 #define FCLR FP(0x17,0x020) /*pseudo*/
755 #define FABS FP(0x17,0x020) /*pseudo*/
756 #define FMOV FP(0x17,0x020) /*pseudo*/
757 #define CPYS FP(0x17,0x020)
758 #define FNEG FP(0x17,0x021) /*pseudo*/
759 #define CPYSN FP(0x17,0x021)
760 #define CPYSE FP(0x17,0x022)
761 #define MT_FPCR FP(0x17,0x024)
762 #define MF_FPCR FP(0x17,0x025)
763 #define FCMOVEQ FP(0x17,0x02A)
764 #define FCMOVNE FP(0x17,0x02B)
765 #define FCMOVLT FP(0x17,0x02C)
766 #define FCMOVGE FP(0x17,0x02D)
767 #define FCMOVLE FP(0x17,0x02E)
768 #define FCMOVGT FP(0x17,0x02F)
769 #define CVTQL FP(0x17,0x030)
770 #define CVTQL_V FP(0x17,0x130)
771 #define CVTQL_SV FP(0x17,0x530)
772 
773 #define FTOIT FP(0x1C, 0x70)
774 #define FTOIS FP(0x1C, 0x78)
775 
776 // =========================================
777 
778 // (Mostly) Multimedia Instructions (SS 4.13, Table 4-19(?))
779 
780 #define PERR OPR(0x1C, 0x31)
781 #define UNPKBW OPR(0x1C, 0x34)
782 #define UNPKBL OPR(0x1C, 0x35)
783 #define PKWB OPR(0x1C, 0x36)
784 #define PKLB OPR(0x1C, 0x37)
785 #define MINSB8 OPR(0x1C, 0x38)
786 #define MINSW4 OPR(0x1C, 0x39)
787 #define MINUB8 OPR(0x1C, 0x3A)
788 #define MINUW4 OPR(0x1C, 0x3B)
789 #define MAXUB8 OPR(0x1C, 0x3C)
790 #define MAXUW4 OPR(0x1C, 0x3D)
791 #define MAXSB8 OPR(0x1C, 0x3E)
792 #define MAXSW4 OPR(0x1C, 0x3F)
793 
794 // =========================================
795 
796 // Generic PALcode format instructions
797 
798 // Specific PALcode instructions
799 
800 #define HALT SPCD(0x00,0x0000)
801 #define DRAINA SPCD(0x00,0x0002)
802 #define BPT SPCD(0x00,0x0080)
803 #define CALLSYS SPCD(0x00,0x0083)
804 #define CHMK SPCD(0x00,0x0083)
805 #define IMB SPCD(0x00,0x0086)
806 #define CALL_PAL PCD(0x00)
807 #define PAL PCD(0x00) /*alias*/
808 #define PAL19 PCD(0x19)
809 #define PAL1B PCD(0x1B)
810 #define PAL1D PCD(0x1D)
811 #define PAL1E PCD(0x1E)
812 #define PAL1F PCD(0x1F)
813 
814 // Hardware and Hardware memory (hw_{ld,st}) instructions
815 // These are essentially instruction classes. Implementations
816 // provide *many* variations of each instruction.
817 
818 #define HW_MFPR PCD(0x19) /* Move data from processor register */
819 #define HW_LD PCD(0x1B) /* Load data from memory */
820 #define HW_MTPR PCD(0x1D) /* Move data to processor register */
821 #define HW_REI PCD(0x1E) /* Return from PALmode exception */
822 #define HW_ST PCD(0x1F) /* Store data in memory */
823 
824 // ==========================================================================
825 
826 // Masks for looking at register operands in Alpha instructions
827 
828 #define REG_A_MASK 0x03e00000 /* Register format; bits 25-21 */
829 #define REG_A_SHIFT 21
830 #define REG_A(INSN) (((INSN) & REG_A_MASK) >> REG_A_SHIFT)
831 
832 #define REG_B_MASK 0x001f0000 /* Register format; bits 20-16 */
833 #define REG_B_SHIFT 16
834 #define REG_B(INSN) (((INSN) & REG_B_MASK) >> REG_B_SHIFT)
835 
836 #define REG_C_MASK 0x0000001f /* Register format; bits 4-0 */
837 #define REG_C_SHIFT 0
838 #define REG_C(INSN) (((INSN) & REG_C_MASK) >> REG_C_SHIFT)
839 
840 // Masks for looking at immediates in Alpha instructions.
841 
842 // immediate:
843 // literal for operate instructions: If bit <12> of the instruction is
844 // 1, an 8-bit zero-extended literal constant is formed by bits
845 // <20:13> of the instruction. The literal is interpreted as a
846 // positive integer between 0 and 255 and is zero-extended to 64 bits.
847 #define IMM_MASK 0x001fe000 /* bits 20-13 */
848 #define IMM_SIGN 0x00000000 /* unsigned */
849 #define IMM_SHIFT 13
850 #define IMM(INSN) (((INSN) & IMM_MASK) >> IMM_SHIFT)
851 
852 // mem_disp:
853 // memory displacement: 16-bit sign-extended displacement for load/stores.
854 #define MEM_DISP_MASK 0x0000ffff /* bits 15-0 */
855 #define MEM_DISP_SIGN 0x00008000 /* bit 15 */
856 #define MEM_DISP_SHIFT 0
857 #define MEM_DISP(INSN) (((INSN) & MEM_DISP_MASK) >> MEM_DISP_SHIFT)
858 
859 // br_disp:
860 // branch displacement: 21-bit displacement is treated as
861 // a longword offset. This means it is shifted left two bits (to
862 // address a longword boundary), sign-extended to 64 bits, and added
863 // to the updated PC to form the target virtual address. Overflow is
864 // ignored in this calculation. The target virtual address (va) is
865 // computed as follows: va <-- PC + {4*SEXT(Branch_disp)}
866 #define BR_DISP_MASK 0x001fffff /* bits 20-0 */
867 #define BR_DISP_SIGN 0x00100000 /* bit 20 */
868 #define BR_DISP_SHIFT 0
869 #define BR_DISP(INSN) (((INSN) & BR_DISP_MASK) >> BR_DISP_SHIFT)
870 
871 // ==========================================================================
872 
873 // Register names: see Tru64 UNIX Assembly Language Programmer's
874 // Guide. Copyright (c) 2000 Compaq Computer Corporation.
875 
876 // There are 32 integer registers (R0 through R31), each 64 bits wide.
877 // R31 always contains the value 0.
878 //
879 // There are 32 floating-point registers ($f0 to $f31), each of which
880 // is 64 bits wide. Each register can hold one single-precision
881 // (32-bit) value or one double-precision (64-bit) value.
882 // Floating-point register $f31 always contains the value 0.0.
883 
884 #define REG_V0 0 /* $v0-v1: Used for expr. eval. and to hold int type fnct */
885  /* results. Not preserved across procedure calls */
886 #define REG_T0 1 /* $t0-t7: Temporary registers used for expr. eval. Not */
887 #define REG_T1 2 /* preserved across procedure calls. */
888 #define REG_T2 3
889 #define REG_T3 4
890 #define REG_T4 5
891 #define REG_T5 6
892 #define REG_T6 7
893 #define REG_T7 8
894 
895 #define REG_S0 9 /* $s0-s5: Saved registers. Preserved across procedure */
896 #define REG_S1 10 /* calls. */
897 #define REG_S2 11
898 #define REG_S3 12
899 #define REG_S4 13
900 #define REG_S5 14
901 
902 #define REG_FP 15 /* $fp or $s6: Contains the frame pointer (if needed); */
903 #define REG_S6 15 /* otherwise a saved register (such as s0-s5) */
904 
905 #define REG_A0 16 /* $a0-a5: Used to pass the first six integer type actual*/
906 #define REG_A1 17 /* arguments. Not preserved across procedure calls. */
907 #define REG_A2 18
908 #define REG_A3 19
909 #define REG_A4 20
910 #define REG_A5 21
911 
912 #define REG_T8 22 /* $t8-t11: Temporary registers used for expr. eval. */
913 #define REG_T9 23 /* Not preserved across procedure calls. */
914 #define REG_T10 24
915 #define REG_T11 25
916 
917 #define REG_RA 26 /* $ra: Contains the return address. Preserved across */
918  /* procedure calls. */
919 #define REG_PV 27 /* $pv: Contains the procedure value and used for expr. */
920  /* eval. Not preserved across procedure calls. */
921 #define REG_AT 28 /* $at: AT Reserved for the assembler. Not preserved. */
922 #define REG_GP 29 /* $gp: Contains the global pointer. Not preserved. */
923 #define REG_SP 30 /* $sp: Contains the stack pointer. Preserved. */
924 #define REG_31 31 /* $31: always 0 */
925 
926 // Automatically accessed by relevant instructions
927 //#define REG_PC 32 /* Program Counter */
928 
929 // The Program Counter (PC) is a special register that addresses the
930 // instruction stream. As each instruction is decoded, the PC is
931 // advanced to the next sequential instruction. This is referred to as
932 // the updated PC. Any instruction that uses the value of the PC will
933 // use the updated PC. The PC includes only bits <63:2> with bits
934 // <1:0> treated as RAZ/IGN. This quantity is a long-word-aligned byte
935 // address. The PC is an implied operand on conditional branch and
936 // subroutine jump instructions. The PC is not accessible as an
937 // integer register.
938 
939 // ==========================================================================
940 
941 
942 #endif