Architecture
This is a closed-book exam. Answer all of the questions. Be concise in your answers. You will receive partial credit for partially correct answers, but extraneous remarks may count against you.
A memory reference can suffer from three different types of misses: a TLB miss, a cache miss, and a page fault. Is it possible for a memory reference to incur a TLB miss but not a cache miss? If not, explain why not. If so, briefly sketch a program that incurs more TLB misses than cache misses.
Assume a tape drive with a sustained transfer rate of 500 KBytes/second and a burst rate of 4 MBytes/second is attached to the SCSI. You want to attach disk drives to the same bus, each with a sustained transfer rate of 6 MBytes/second and a burst rate of 20 MBytes/second. How many disk drives can you attach to the bus and expect to be able to run all devices simultaneously at full speed? What will the bus utilization be in that case? (You may use 1K=1,000 and 1M=1,000,000 to simplify your calculations.)
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